Dec. 08, 2005
IBM's DeveloperWorks website has published a paper on the Xbox 360 CPU. The paper offers an introductory yet technical look at the chip's design and development process, core architecture, frontside bus architecture, debugging interfaces, and more. It was given by Chief Engineer Jeff Brown at the Fall Processor Forum.
According to Brown, the Xbox 360 processor project involved demanding requirements for performance, cost, and production deadlines. Brown's team jumpstarted development by leveraging existing PowerPC and subsystem technology, he says.
The Xbox 360 chip uses three of the fastest-available (3.2 GHz) PowerPC cores, in a cache-coherent symmetrical multiprocessing architecture with a 1MB L2 cache and a frontside/physical bus speed of 5.4 GHz. In addition to supporting the full 64-bit PowerPC ISA (instruction set architecture), each core is specialized with "VMX128" extensions, similar to VMX instructions in G4 and G5 CPUs, Brown writes.
The chip offers a variety of debugging features, including JTAG, a POST monitor, and a serial EEPROM interface. It also uses extensive clock gating to save power.
Though labeled "introductory" by DeveloperWorks, Brown's article offers considerable technical detail about the Xbox 360's cores, debugging facilities, frontside bus architecture, and more. Read Brown's Xbox 360 whitepaper here.http://www-128.ibm.com/developerworks/powe...nxw09XBoxDesign